Design a Special Adaptive Router for FC-Mesh Architecture to Reduce Power Consumption at the Chip Level

Abstract

      Excessive power consumption is one of the most significant problems facing networks on chip (NoC), especially when considering scalability. It is essential to investigate power issues and reduce their consumption during design for all components of the chip architecture, this can be done by making modifications on the components that make up the network, the most prominent of which are perhaps the network routers, given that they are the backbone of the communications infrastructure within the chip. Based on this, our paper proposes an efficient buffer-less router design using an adaptive routing design technique that addresses the connectivity and complexity of the network nodes. The justifications for the design stem from the cost of buffers and their high power consumption, as well as the simplicity of the design. Furthermore, the router design takes into account the uniqueness of each node in terms of its location and complexity, thus minimizing resource consumption in the form of unused ports. The proposed router was implemented on the Full-Connected Mesh (FC-Mesh) architecture. Simulation results for FC-Mesh network architecture, comparing the proposed design method with a non-adaptive buffering approach, showed that the proposed method reduced power consumption by 22.9% to 30.4%, depending on the traffic pattern. Furthermore, it increased data transmission speed, resulting in a throughput increase of up to 11.3% and a latency reduction of up to 9.6% under various network operating conditions.